[Samsung Unveils BV-NAND, zHBM, and zNAND-O: 10x Density, 3x Energy Efficiency Over HBM5]

Samsung unveiled the V10 Bonding V-NAND (BV-NAND) prototype and the industry’s first conceptual models of zHBM and zNAND-O architectures at the Future of Memory and Storage (FMS) conference held in Santa Clara, California, US. The BV-NAND chip features over 400 layers and adopts a novel wafer bonding architecture to enhance memory density and performance. Compared with the previous-generation V9 NAND, it delivers approximately 58% higher memory density, along with significant improvements in read, write, and I/O performance, meeting the demands of AI systems for higher-capacity, more energy-efficient memory solutions.

For the zHBM and zNAND-O architectures, Samsung achieves greater data capacity in a smaller footprint by vertically stacking memory cells. Unlike conventional HBM, which is packaged side-by-side with AI processors, zHBM stacks memory vertically on top of the AI accelerator, thereby shortening data transfer distances, increasing bandwidth, and boosting energy efficiency. Samsung stated that its wafer bonding technology is expected to deliver more than 10 times the memory density of conventional HBM5, improve energy efficiency by 3 times, and reduce thermal resistance by more than half.