In the post-Moore era, advanced packaging attracts attention, AMD leads the chiplet trend, A-share closed test plate is ready to go.

Chaowei (AMD) CEO Su Zifeng said today that AMD has worked closely with TSMC to develop the industry-leading 3D chiplet (small chip / chip / bare chip) technology and start producing future high-end operational (HPC) products using 3D chiplet technology by the end of this year.

It is understood that AMD has booked 5 nm and 3 nm production capacity with TSMC in the next two years, and is expected to launch a 5 nm Zen4 architecture processor in 2022 and a 3 nm Zen5 architecture processor in 2023-2024, which will become the largest customer of TSMC's 5 nm and 3 nm high performance computing products.

AMD leads chiplet trend

Chiplet is a kind of advanced packaging technology, which refers to the dispersion of large-size, multi-core designs into smaller chips. It is not a new concept. As early as 2014 / 2015, Fablessers proposed a similar design architecture.

The background of its proposal is that in the post-Moore era, the semiconductor advanced process continues to move towards 7nm/5nm or even below, and the difficulty, cost and development time of wafer design and manufacturing process miniaturization are increasing by leaps and bounds. Through the high-density interconnection of chiplet architecture and advanced packaging, the same level of performance can be achieved at lower cost.

In this way, chiplet design has gradually become the mainstream. Fabless and IDM companies, including Hisilicon, Marvell, Xilinx, AMD to Intel, actively promote the development of chiplet ecology.

AMD is undoubtedly the leader of this wave of chiplet.

When the company fully adopted chiplet technology in 2019, Su Zifeng said that AMD would still work with TSMC and other wafer foundry to continue to miniaturize the process, and Moore's law was still valid, but at a significantly slower pace. In order to achieve efficiency improvement in the process miniaturization, we can achieve the goal through innovative chip architecture, heterogeneous integration platform, chiplet system-level packaging and other innovative methods.

Currently, AMD has built its own chiplet ecosystem, producing Ryzen and Epycx86 processors.

The local semiconductor sector ushered in a golden period of accelerated catch-up.

It is very important for domestic semiconductor enterprises to grasp these advanced packaging technologies.

On May 14, the 18th meeting of the National leading Group on Science and Technology system Reform and Innovation system Construction was held in Beijing. The meeting discussed the potential subversive technologies of integrated circuits for the post-Moore era.

In this regard, Tianfeng Securities analyst Pan Yun believes that with the advent of the post-Moore era, the local semiconductor plate ushered in an accelerated catch-up golden period, advanced packaging is potentially subversive, and the 2025 market is expected to reach $43 billion.

Yole predicts that advanced packaging is expected to grow by 7 per cent CAGR between 2019 and 2025, reaching $43 billion by 2025. In the three years from 2018 to 2020, the proportion of advanced packaging in China's sealing and testing industry is about 35%, 37% and 40% respectively, and it is estimated that the proportion of advanced packaging products will exceed 45% after 2022.

In addition, like chiplet, system-level packaging (SiP) also has the advantages of short R & D cycle and space saving.

Science and Technology Innovation Board Daily combs related companies:

Domestic enterprises that have made great progress in the field of advanced packaging include Changdian Technology, Tonfu Micro Power, Jingfang Technology, Huatian Technology and so on.

Among them, Tong Fu Micro Power deeply binds two subsidiaries of AMD, Tong Fu Chao Wei Suzhou and Tong Fu Chao Wei Penang, accounting for 100% of the advanced packaging products, including high-end packaging technologies such as FCBGA, FCPGA, FCLGA and MCM.

Huatian Technology has independently developed advanced packaging technologies such as multi-chip packaging (MCP) technology, multi-chip stacking (3D) packaging technology, thin high-density integrated circuit technology, integrated circuit packaging anti-delamination technology, 16nm wafer-level bump technology, and saw filter packaging technology based on C2W and TSV.

Changdian Technology is on a par with the first Sunmoon Group in the world in terms of advanced packaging technology coverage, with industry-leading high-end packaging technologies such as SiP, WLCSP, FC, eWLB, PiP, PoP and 2.5mp 3D.

Jingfang Technology is the optical track TSV-CIS closed test leader, with 8-inch, 12-inch wafer-level chip size packaging technology scale mass production packaging line, covering wafer-level to chip-level one-stop integrated packaging service capabilities.