SMM News: during the VLSI Symposium (VLSI Symposium held in Tokyo, Japan earlier this month, TSMC showed off a small chip, (chiplet) This, which it designed. In terms of basic parameters, This adopts 7nm process, 4.4x6.2mm (27.28mm), CoWos (wafer substrate package), dual-chip structure, one built-in four Cortex A72 cores, the other built-in 6MiB three buffers.
The chip uses a dual-chip design, this technology can be extended by adding additional PHY, the chip between different units and between different chips can form interconnection. Each chip has 15 metal layers, and the mold itself is only 4.4mm x 6.2mm (27.28mm). TSMC uses four Arm Cortex-A72 cores, for turbo frequency greater than 4GHz voltage operation, equipped with high-performance units (7.5T, 3p + 3n) and custom design of level 1 cache unit, this module has two L2 cache blocks, each 1MiB, these are implemented using their high current bit units and run at half speed. In addition, there is a large 6MiB L3 cache, implemented using high-density bit units, and running at 1/4 speed.
At 1.20 voltage, the Cortex core can reach 4GHz, and the highest measured value is 4.2GHz (1.375V). TSMC said the chip was designed for high-performance computing platforms, which explains why its dominant frequency is so amazing.