SMM Network News: semiconductor chip packaging technology after years of development, there are hundreds of packaging types today.
Most applications require more general-purpose single-component packaging for integrated circuits and other components, such as resistors, capacitors, antennas, and so on. However, as the semiconductor industry develops smaller, more powerful devices, "system packaging" (SiP)-type solutions are becoming the first choice, with all components in a single package or module.
Although the type of package can be easily divided into lead frame package, substrate package or wafer level package, it is more complex to choose the package that suits all your needs, and it is necessary to evaluate and balance the application requirements. To make the right choice, you have to understand the impact of multiple parameters, such as heat demand, power, connectivity, environmental conditions, PCB assembly capabilities, and, of course, cost.
This article describes seven different key requirements that need to be evaluated in order to select the appropriate packaging technology.
Common Packaging Technology
Over the years, packaging technology has continued to develop, today, through the use of different connection and assembly methods, there are a variety of packaging types to choose from. This paper mainly discusses the four most commonly used packages: BGA, QFN, WLCSP and eWLB.
BGA (Ball Gate Array) is a packaging option for IC that requires a large number of I / O connections. The advantages of BGA include low inductance and good heat dissipation choice. The disadvantage is that detection and fault detection are difficult and may cost more than other packages such as QFN.
QFN (square flat pinless package) is one of the most popular semiconductor packages at present. It has the advantages of low cost, small shape, good electrical and thermal performance. The disadvantages of QFN include a small number of pins, potential oxidation problems, and reliability in long life and harsh environments.
WLCSP (Fan-type wafer-level CSP) is essentially a raised bare chip, so it can provide the smallest possible package size because it is the same size as the chip. WLCSP has reasonable low cost, small size and good electrical performance, but may not be suitable for applications with high number of pins.
EWLB (embedded wafer level ball gate array) uses interpolation wafer under the original wafer to realize fan out and more interconnection wiring space. In this way, a larger bare chip area is produced, and the interconnection problem of WLCSP is solved. EWLB is becoming the first choice for consumer ASIC and wireless ASIC.
Application category: cost vs performance
Your target application is the main driver of packaging choices. How is your application environment? Do you develop a system on a chip, or do you use ASIC as a key component of the system?
These questions will help you determine the type of package-can you use a wafer-level or chip-size package, or is it more appropriate to use a standard, more accessible BGA or QFN type package?
Application performance requirements and corresponding encapsulation options can be broadly divided into three categories:
High-end application requirements are usually related to high-speed, high-power chips with a large number of connections (a large number of pin outputs). These devices require advanced packaging requirements to meet the needs of small pad spacing, high-speed signals, and decoupling, which can be achieved through FC-BGA (flip chip BGA) or newer packages, such as embedded wafer level ball grid array (eWLB).
Mid-range applications often need to be able to solve thermal enhancement problems and use cost-effective plastic packaging technologies-typically BGA and QFN packaging. The high end of middle-end applications is chip-level and wafer-level packaging, which is suitable for system packaging and multi-chip module packaging.
Entry-level applications include high-yield applications, where cost is the main driver, not performance. For example, devices for notebook and mobile phone applications typically require smaller wafer-level and chip-size packages.
Number of pins and I / O
The number and position of the input and output connections of the device are the key factors to be considered in determining the packaging requirements. In addition, in the aspects of power connection, high-speed data input and output, grounding connection and control and monitoring signals, it is necessary to clearly identify the type of interconnection, which is related to the chip and packaging layout.
There are a lot of pins. If you have a large number of pins, such as a 1000-pin package, your best option is a standard BGA package, which provides this I / O capability, because the overall package size can reach 50 to 60 square millimeters.
The number of pins is small. For a low number of pins, such as 50 pins, your choice may be QFN or WLCSP encapsulation. However, WLCSP has limits on heat dissipation in the package. In the case of heat generation (for example, a fast switch) or the need for good signal grounding, the QFN is a better packaging option because it has a "built-in" metal base pad.
Overall Arrangement. The other parameter is the location of the I / O. If I / O is located on the periphery around the bare sheet, wire bonding can be carried out quickly, simply and reliably as long as the bare sheet and the package pad have sufficient surface area. If I / O is distributed in different areas of the chip surface, making it difficult to bond outward from the center of the chip, then flip chip packaging provides a way to connect directly to the package substrate (usually multi-layer PCB). There will be no problem of overlapping naked pieces.
Advances in chip technology have led to the continuous production of smaller, faster chips, which means that chips are also generating more heat. Therefore, thermal management is the key packaging factor to optimize chip performance.
Thermal management ensures the reliability and lasting operation of the chip. For example, if the temperature is kept low, interconnections (such as chip bonding materials, wire bonding or flip chip balls) are more reliable. For example, if an ASIC chip is placed on a substrate using epoxy resin and the temperature is too high, the epoxy resin softens and may melt, causing the ASIC to physically move, making the package unreliable. Overheating may also have a negative effect on the RF frequency and degrade the performance of the device.
Thermal management is also one of the cost factors, depending on the type of device and package selected. Different heat dissipation processes and methods are associated with different types of packaging. For example, BGA packaging typically provides a lower cost and better thermal management solution in the package because it has a larger area available for heat dissipation. Smaller chips tend to create a thermal environment and may be more expensive in thermal management solutions, requiring external radiators or other cooling options.
The BGA package has two thermal conduction pad options, such as conductive through holes or built-in metal substrates, for adequate thermal management. Some options for heat-enhanced BGA packaging can build a metal cap, on it to establish a heat conduction path between the IC device and the metal cap, providing good heat dissipation.
The design of QFN package makes them have the solid metal chip pad as the base of the package, and the naked chip combines with it. This makes the heat dissipation from the chip to the PCB very good.
Bare sheet add-on material. Bonding the chip to the substrate using a thermal conductive adhesive, such as silver-filled epoxy instead of ordinary epoxy, helps eliminate heat. In addition, there are some new technologies, such as silver sintering technology, an interconnection method with high working temperature, high thermal conductivity and high conductivity. These materials usually work well in QFN packaging, but they do not work well in BGA packaging because of their structure.
Chip size and wafer level package. The thermal management in these packages is mainly done on the back of the chip or in the chip size package, at the top of the exposed chip.
High speed signal / RF
Radio frequency, wireless and high-speed digital design have specific requirements, which affect the choice of packaging. The parameter effect of interconnection in package can significantly reduce the signal speed and frequency.
Wire bonded vs flip chip. In RF devices, key design considerations include inductance, capacitance and resistance, which are affected by the signal speed in and out of the device. These problems also affect package selection, mainly between flip chips and wire bonding interconnects. Flip chips provide better RF performance and can achieve higher frequencies with lower inductors. On the other hand, wire bonding can add randomly varying inductors at each place where the RF input or output frequency is high.
Encapsulates the layout. At radio frequency, the signal propagates along the surface rather than in the conductor. Therefore, the way of packaging has an important impact on the device. For example, high-speed amplifier chips, RF transistors, and diodes usually cannot be placed in a "standard" plastic package because the packaging material affects the speed of the chip. Therefore, the chip should be placed in a cavity QFN or BGA package.
High frequency signals (1GHz and above) may require the layout of the interconnect to have an isolated signal path, the so-called "ground-signal-ground" interconnect. Here, the requirement for two grounding connections for each signal I / O will affect the size and layout of the package.
In addition, the level and timing of high-speed ASIC, signals will be affected by the length of the conductor they pass through. For example, if you are using BGA encapsulation and have a longer pin pointing to one point and a shorter pin pointing to the next, the timing of the signal will vary greatly. This must be overcome by more consideration of the initial design of the package substrate to adapt to high-speed RF devices.
The dielectric material of BGA substrate is also the key factor of RF chip. For example, high-performance liquid polymer substrates, such as Rogers laminates, are more suitable for use as substrates for BGA packaging in RF designs than standard FR4 PCB materials.
PCB assembly and the method of connecting packaged ASIC chips to circuit boards require several processes that may affect reliability, so these processes should be taken into account in determining ASIC packaging.
Depending on the type of package you choose, you need to make sure that you find a supplier with the correct PCB assembly process to ensure that the projects you complete are of the highest quality. Advanced package components cannot be handled by any electronic manufacturing service company. Your choice should be able to accommodate the right spacing, both small package and large package size.
For example, chip size packages, wafer level packages, and, of course, bare chip flip chips all require heating and pressure processes to connect them directly to the PCB. Therefore, the assembler needs to have advanced PCB assembly capabilities to achieve accurate location processing and appropriate advanced processes to ensure that these small size components are reliably connected to the circuit board.
On the other hand, if the package is a multi-I / O ball grid array (BGA) package with ball spacing (for example, 0.5mm or less), the process requires high quality PCB assembly capability, high precision calibration and professional welding process. To produce reliable and robust results.
QFN packages have many advantages, but they also have some important manufacturing and reliability issues at the PCB level, so they need more professional processes to assemble. Because the package adopts metal "embedded (slug)" substrate with external contact pad, the assembly process is prone to defects, such as short circuit, cavity, opening and filling defects, when used in combination with lead-free welding process, The problem of forming holes becomes more difficult.
Specific environmental or mechanical requirements often determine the type of packaging required for the application. Consumer products have the simplest requirements (see table below) because packaging is often cost-driven rather than environment-driven. At this point, plastic packaging is preferred, but even here, the demand for shock and vibration resistance is a limiting factor of the available types.
However, if the selected applications and systems need to be protected from moisture or chemical effects, such as in many medical and aerospace applications, the need for package airtightness is driven. In this case, the only option may be to use a specific type of package, such as sealed metal or ceramic packaging, to protect the ASIC device.
In automotive applications, packaging needs to be able to withstand temperature, vibration and shock levels that now meet the requirements of defense and aerospace (see MIL standard). However, because cost is a key driver of cars, the automotive industry has improved the performance of standard packaging so that QFN and some BGA-type parts can be accepted.
In the space industry, the next generation of spacecraft and satellites need high-speed, low-cost ASIC devices. Here, applications require low cost and light weight, but can also withstand high gravity, mechanical shock and pressure. The potential solution may be plastic packaging, although these types are not sealed. This need urges these applications to find new ways to seal the entire system in order to overcome packaging defects.
The following table provides some environmental requirements for different industries and some examples of potential encapsulation solutions.
Specific application requirements
In most cases, specific application requirements determine the type and form of encapsulation. However, many new applications, such as handheld devices, the next generation of wafer-level ASIC devices, such as silicon through-hole (TSV), may not require packaging. In this case, the direct bare chip connection / flip chip process will be used.
ASIC typically supports functional devices such as sensors and LED, in which packaging is not the above type of standard, but the packaging or housing of electronic products must be suitable for the specific shape and space defined by the application. This approach can be used in typical applications in automotive, aerospace and industrial applications. For example, a ASIC chip may need to be suitable for a specific space, such as a power module or a sensor control system housing.
In other cases, such as when building an automobile module, you can use a system-level encapsulation (SiP), to bind multiple IC and peripherals in a single package. Custom ceramic packages, such as Pin Grid arrays or metal can module packages, can be used here.
The next generation of SiP and emerging applications are considering the use of three-dimensional packaging technologies, such as molded interconnect devices (3DMID) and 3D multi-layer stack packaging units, which are customized for application-specific solutions.
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